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| 128MB, 256MB, 512MB Unbuffered DIMM SDRAM SDRAM Unbuffered Module 168pin Unbuffered Module based on 256Mb E-die 62/72-bit Non ECC/ECC Revision 1.4 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (June, 2003) - First release Revision 1.1 (September, 2003) - Corrected Typo Revision 1.2 (February, 2004) - Corrected typo. Revision 1.3 (March. 2004) - Modified DC Characteristics Notes. Revision 1.4 (May, 2004) - Added Note 5. sentense of tRDL parameter SDRAM Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM 168Pin Unbuffered DIMM based on 256Mb E-die (x8, x16) Ordering Information Part Number M366S1654ETS-C7A M366S3253ETS-C7A M366S3253ETU-C7A M374S3253ETS-C7A M374S3253ETU-C7A M366S6453ETS-C7A M366S6453ETU-C7A M374S6453ETS-C7A M374S6453ETU-C7A Density 128MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB Organization 16M x 64 32M x 64 32M x 64 32M x 72 32M x 72 64M x 64 64M x 64 64M x 72 64M x 72 Component Composition 16Mx16(K4S561632E) * 4EA 32Mx8(K4S560832E) * 8EA 32Mx8(K4S560832E) * 8EA 32Mx8(K4S560832E) * 9EA 32Mx8(K4S560832E) * 9EA 32Mx8(K4S560832E)*16EA 32Mx8(K4S560832E)*16EA 32Mx8(K4S560832E)*18EA 32Mx8(K4S560832E)*18EA 54-TSOP(II) Component Package SDRAM Height 1,000mil 1,375mil 1,125mil 1,375mil 1,125mil 1,375mil 1,125mil 1,375mil 1,125mil Operating Frequencies 7A @CL3 Maximum Clock Frequency CL-tRCD-tRP(clock) 133MHz(7.5ns) 3-3-3 @CL2 100MHz(10ns) 2-2-2 Feature Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * * * * * Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PIN CONFIGURATIONS (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 SDRAM Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD Note : 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Pin Description Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 ~ 3 CKE0, CKE1 CS0 ~ CS3 RAS CAS WE Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable Function Address input (Multiplexed) VDD VSS VREF REGE SDA SCL SA0 ~ 2 DU NC Pin Name DQM0 ~ 7 DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Function * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PIN CONFIGURATION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. SDRAM Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic. CKE Clock enable A0 ~ A12 Address BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 Bank select address Row address strobe Column address strobe Write enable Data input/output mask REGE Register enable DQ0 ~ 63 CB0 ~ 7 VDD/VSS Data input/output Check bit Power supply/ground Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM 128MB, 16Mx64 Module (M366S1654ETS) (Populated as 1 bank of x16 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS0 DQM0 LDQM * DQM4 CS LDQM CS SDRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM U0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM U2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS2 DQM2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 * DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM6 LDQM CS LDQM CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM U1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM U3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss * * * * SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SCL 47K WP A0 SDA A1 A2 SA0 SA1 SA2 10 CLK0/2 15pF * * U0/U2 U1/U3 Every DQpin of SDRAM 10 CLK1/3 Two 0.1uF Capacitors per each SDRAM To all SDRAMs 10pF Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM SDRAM 256MB,32Mx64 Non ECC Module(M366S3253ETS(U))(Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS0 DQM0 DQM * DQM4 CS DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS2 DQM2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM6 DQM CS DQM CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM U6 DQM CS CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 Serial PD SCL 47K WP A0 SDA A1 A2 SA0 SA1 SA2 * 10 CLK0/2 * * U0/U2 U4/U6 U1/U3 U5/U7 10 DQn VDD Vss * * * * One 0.1uF and one 0.22 uF Cap. To all SDRAMs per each SDRAM CLK2/3 Every DQpin of SDRAM 3.3pF*1 10 10pF Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM SDRAM 256MB, 32Mx72 ECC Module (M374S3253ETS(U)) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS0 DQM0 * DQM4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 CS U0 DQM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 CS U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS2 DQM2 CS U1 DQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 CS U6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U2 DQM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 CS U7 * DQM CS U3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U8 DQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U4 Serial PD SCL 47K WP A0 SDA A1 A2 SA0 SA1 SA2 A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss * * * * SDRAM U0 ~ U8 10 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 Every DQpin of SDRAM CLK1/3 One 0.1uF and one 0.22 uF Cap. To all SDRAMs per each SDRAM 3.3pF*1 CLK0/2 * * U0/U3 U5/U7 U1/U4 * * U6/U8 U2 *1 : For 4 loads, CLK2 only. 10 10pF Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM SDRAM 512MB, 64Mx64 Non ECC Module (M366S6453ETS(U)) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 * CS DQM * DQM4 CS * DQM CS DQM CS * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM U0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM U8 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * U4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U12 CS CS DQM CS DQM CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3 CS2 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U9 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U13 * DQM * CS DQM * DQM6 CS * DQM CS DQM CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM U2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM U10 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM U6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM U14 CS CS CS CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U11 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Serial PD U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U7 10 CKE1 * 10K SDRAM U8 ~ U15 10 CLK0/1/2/3 SCL 47K WP A0 SDA A1 A2 SA0 SA1 SA2 * * * * U0/U1/U2/U3 U4/U5/U6/U7 U8/U9/U10/U11 U12/U13/U14/U15 DQn VDD Vss * * * * Every DQpin of SDRAM Two 0.1uF Capacitors per each SDRAM To all SDRAMs 3.3pF Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM SDRAM 512MB, 64Mx72 ECC Module (M374S6453ETS(U)) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * CS U0 * DQM4 * DQM CS U5 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U9 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 * DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS3 CS2 DQM2 CS U1 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U10 DQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 CS U6 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U11 * DQM CS U7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U16 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * CS U3 * DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U12 * DQM CS U8 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U17 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U13 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Serial PD A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss * * * * SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 CKE1 SDRAM U0 ~ U8 VDD SCL 47K WP A0 SDA A1 A2 10K * SDRAM U9 ~ U17 10 CLK0/1/2/3 SA0 SA1 SA2 * * * * 3.3pF*1 U1/U3/U0/U4 U6/U7/U5/U8 U10/U12/U9/U13 U15/U16/U14/U17 U2/U11 Every DQpin of SDRAM Two 0.1uF Capacitors per each SDRAM To all SDRAMs *1 : For 4 loads, CLK2 & CLK3 only. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.0 * # of component 50 SDRAM Unit V V C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT M366S1654ETS Min 15 15 15 10 10 8 9 Max 25 25 25 13 15 10 12 M374S3253ETS(U) Min 28 28 28 18 18 8 9 Max 50 50 50 25 30 10 12 M366S3253ETS(U) Min 25 25 25 15 15 8 9 Max 45 45 45 21 25 12 12 M366S6453ETS(U) Min 45 45 25 15 15 10 13 M374S6453ETS(U) Min 50 50 28 18 18 13 13 Max 95 95 50 25 30 20 18 Max 85 85 45 21 25 15 18 Unit pF pF pF pF pF pF pF Unit pF pF pF pF pF pF pF Parameter Input capacitance (A0 ~ A11) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance (CS) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) Pin Input capacitance (A0 ~ A11) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance (CS) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM DC CHARACTERISTICS M366S1654ETS (16M x 64,128MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 360 8 8 80 mA 40 25 25 100 100 mA mA mA SDRAM Unit mA mA Note 1 ICC4 ICC5 ICC6 520 720 12 mA mA mA 1 2 M366S3253ETS(U) (32M x 64, 256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 640 16 16 160 mA 80 50 50 200 200 mA mA mA Unit mA mA Note 1 ICC4 ICC5 ICC6 800 1,440 24 mA mA mA 1 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM DC CHARACTERISTICS M374S3253ETS(U) (32M x 72, 256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 720 18 18 180 mA 90 54 54 225 225 mA mA mA SDRAM Unit mA mA Note 1 ICC4 ICC5 ICC6 900 1,620 27 mA mA mA 1 2 M366S6453ETS(U) (64M x 64, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 840 32 32 320 mA 160 96 96 400 400 mA mA mA Unit mA mA Note 1 ICC4 ICC5 ICC6 1,000 1,620 48 mA mA mA 1 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM DC CHARACTERISTICS M374S6453ETS(U) (64M x 72, 512MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 945 36 36 360 mA 180 108 108 450 450 mA mA mA SDRAM Unit mA mA Note 1 ICC4 ICC5 ICC6 1,125 1,845 54 mA mA mA 1 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 SDRAM Unit V V ns V 3.3V Vtt = 1.4V 1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50 50 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version 7A 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 2.5 2.5 1.5 0.8 1 5.4 6 ns ns ns ns ns ns tSAC Symbol Min tCC 7.5 10 5.4 6 ns ns 7A Max 1000 ns Unit SDRAM Note 1 1,2 2 3 3 3 3 2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H CKEn-1 CKEn CS RAS CAS SDRAM (V=Valid, X=Dont care, H=Logic high, L=Logic low) WE DQM BA0,1 A10/AP A0 ~ A9, A11, A12 Note H H X H L H X X L L L H L L H X L H L L H X H L L H H X H H X X OP code X 1,2 3 3 X X X V V X Row address L H Column address 3 3 Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable L L 4 4,5 4 4,5 6 H H H X X X L L L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V X X X V L H X Column address V X L H X H L H L H L X X X X X X V X X 7 X H L L H H H H L X H L X H X H X H X Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 16Mx64 (M366S1654ETS) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.000 (25.40) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.100 Max (2.54 Max) (5.08 Min) 0.200 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 16Mx16 SDRAM, TSOPII SDRAM Part No. : K4S561632E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 32Mx64 (M366S3253ETS) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.089 (2.26) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.375 (34.925) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.100 Max (2.54 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS :32Mx64 (M366S3253ETU) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 0.374 (9.505) 0.096 (2.44) 0.125 (3.18) 5.014 (127.350) 0.089 (2.26) R 0.050+0.04 (R 1.27+0.1/-0.0) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.125 (28.575) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.100 Max (2.54 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 32Mx72 (M374S3253ETS) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.089 (2.26) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.375 (34.925) 0.118 (3.000) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.350 (8.890) 0.0984 0.008 (2.500 0.2) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) A B C 0.700 (17.780) 0.100 Max (2.54 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 0.250 (6.350) 0.250 (6.350) (2.500 0.2) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 32Mx72 (M374S3253ETU) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 0.374 (9.505) 0.096 (2.44) 0.125 (3.18) 5.014 (127.350) 0.089 (2.26) R 0.050+0.04 (R 1.27+0.1/-0.0) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.125 (28.575) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.100 Max (2.54 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 0.250 (6.350) 0.250 (6.350) (2.500 0.2) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 64Mx64 (M366S6453ETS) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.375 (34.925) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.150 Max (3.81 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 64Mx64 (M366S6453ETU) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.125 (28.575) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.150 Max (3.81 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 64Mx72 (M374S6453ETS) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.375 (34.925) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.150 Max (3.81 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PACKAGE DIMENSIONS : 64Mx72 (M374S6453ETU) SDRAM Units : Inches (Millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 1.125 (28.575) 0.118 (3.000) .118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.0984 0.008 (2.500 0.2) A B C 0.700 (17.780) 0.150 Max (3.81 Max) (4.19 Min) 0.165 Min 0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2) 0.250 (6.350) 0.250 (6.350) 0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Detail B Detail C Tolerances : 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E Rev. 1.4 May 2004 |
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